High power doherty amplifier

ABSTRACT

A high power Doherty amplifier circuit having at least one input terminal and at least one output terminal comprising at least one carrier transistor ( 30 ) forming a main amplifier stage; at least one peak transistor ( 32 ) forming a peak amplifier stage; a first input line ( 27 ) connecting the input terminal ( 28 ) to an input ( 29 ) of the carrier transistor ( 30 ); a second input line ( 31 ) connecting the input terminal ( 28 ) to an input ( 63 ) of the peak transistor ( 32 ); a first output line ( 33 ) connecting the output terminal ( 56 ) to an output ( 49 ) of the carrier transistor ( 30 ); and a second output line ( 35 ) connecting the output terminal ( 56 ) to an output ( 75 ) of the peak transistor ( 32 ). A high power Doherty amplifier circuit package comprising a support structure ( 104 ) supporting circuit elements of the Doherty amplifier circuit; at least one input terminal ( 102 ) and at least one output terminal ( 96 ) both terminals being supported on the support structure ( 104 ); at least one carrier transistor ( 92 ) forming a main amplifier stage and at least one peak transistor ( 98 ) forming a peak amplifier stage both transistors being supported on the support structure ( 104 ); a first input network ( 106 ) connecting the input terminal ( 102 ) to an input of the carrier transistor ( 92 ); a second input network ( 100, 114, 116 ) connecting the input terminal ( 102 ) to an input of the peak transistor ( 98 ); a first output network ( 94, 108, 110 ) connecting the output terminal ( 96 ) to an output of the carrier transistor ( 92 ); and a second output network ( 112 ) connecting the output terminal ( 96 ) to an output of the peak transistor ( 98 ), and wherein the input and output networks are artificial transmission lines comprising serial circuits and/or parallel circuits of at least one capacitance and/or at least one inductance.

The present invention relates to a high power Doherty amplifier, inparticular to a high power Doherty amplifier circuit and a high powerDoherty amplifier circuit package.

So-called Doherty type amplifiers are known since a long time and werefirst implemented in vacuum tube amplifiers. Such Doherty amplifiershave a main amplifier stage and a peak amplifier stage, and (quarterwave) transmission lines between various parts of the Doherty amplifier.Well known Doherty amplification techniques require at least two activeamplification devices operating in two different modes, usually A or ABclass for carrier amplifiers, and B or C class for peak amplifiers, andtransformation structures providing the impedance transformation and therequired phase shift.

It is well known that, for Doherty amplifiers, the transformation andphase shifting structures provide a characteristic impedance, comparableto the device output impedance. In case of semiconductor power deviceand power level >5 . . . 10 W this required impedance is in the range of0.5 . . . 3 Ohm.

A design example and results on microstrip line technology are describedin the paper “Optimum design for linearity and efficiency of a MicrowaveDoherty Amplifier using a new load matching technique”. by Youngoo Yangand others, in Microwave Journal, 12, 2001, which discloses a Dohertyamplifier with full load matching circuits of the carrier and peakingamplifiers at both low and high power levels is demonstrated for thefirst time. In the circuit design, sections of transmission lines areinserted in the load matching network for providing apower-level-dependent load impedances. The circuit elements and biaspoints are designed and optimized using a large-signal harmonic balancesimulation to offer simultaneous improvements in linearity andefficiency. Two 1.4 GHz Doherty amplifiers have been implemented usingsilicon LDMOS FETs. The RF performances of the Doherty amplifier-I (acombination of a class B carrier amplifier and a bias-tuned class Cpeaking amplifier) have been compared with those of a class B amplifieralone. The Doherty amplifier-II (a combination of a class AB carrieramplifier and a bias-tuned class C peaking amplifier) has been comparedwith a class AB amplifier alone. The new Doherty amplifiers show animproved linearity as well as higher efficiency. The paper describes amicrostrip line implementation of Doherty technique for transistors.

The U.S. Pat. No. 6,359,513 B1 describes a CMOS class F amplifier usinga differential input to eliminate even-order harmonics, thereby avoidingthe need for circuits that are tuned to the second harmonic. This alsominimizes the sensitivity of the design to changes in the secondharmonic frequency and/or the particular component values selected forthe tuned circuit sensitivity of the particular component valuesselected for the tuned circuit. Third-order harmonics are reduced bycontrolling the phase relationship between the differential inputs.Additional efficiency is achieved by dynamically controlling theimpedance of the amplifier as a function of output power level.

The U.S. Pat. No. 6,359,513 B1 suggests a high efficiency poweramplifier with use of F-class and Doherty amplification techniques. Itssolution is about amplification technique which is operating with asignal, which is limited to the special conditions, such as a “pulsewith duration equal to the one third of the modulated signal cycleperiod”.

The objectives are to reduce the 3-rd harmonics produced by Class Famplifier; to increase the efficiency of a Class F amplifier; to reducethe harmonics and to increase the efficiency in a CMOS embodiment; andto increase the efficiency in a wide range of power in Class Famplifier. These objectives are achieved by providing differential input(180 degree) to eliminate even-order harmonics and avoid the use ofcircuits tuned for second harmonic, phase control between thedifferential inputs to reduce the third harmonics, output matchingcircuits configured for the third harmonics elimination, dynamic loadcontrol at lower output power by providing two additional transistors.

The U.S. Pat. No. 6,329,877 B1 discloses a power amplifier including anin-phase power splitter generating two split signals from an inputsignal, and two amplifiers capable of operating in different modes. Thesplit signals are provided as respective inputs to the two amplifierswhich are coupled through transmission lines such that as the firstamplifier approaches the maximum power it can produce, the output fromthe second amplifier begins to contribute to the power amplifier outputand supplements and modifies the power provided by the first amplifierthereby extending the range of input power over which the poweramplifier delivers output power.

The U.S. Pat. No. 6,329,877 B1 suggests an amplifier arrangement forbattery amplifiers, where the goal is to extend the range of the inputover which the power amplifier delivers output power and where the inputpower is split between the first and the second amplifier equally inpower and at the same phase, the first amplifier is an A classamplifier, the first amplifier may have an output matching networkstructure, the transmission line is of 50 Ohm impedance, the impedanceseen by the first amplifier is growing with the second amplifierstarting to open from the input power.

It is an object of the present invention to provide a high power Dohertyamplifier circuit for high peak power levels and a high power Dohertyamplifier circuit package for compact design and flexibility for Dohertyamplification concept.

To achieve the object of the present invention a high power Dohertyamplifier circuit having at least one input terminal and at least oneoutput terminal comprising at least one carrier transistor forming amain amplifier stage; at least one peak transistor forming a peakamplifier stage; a first input line connecting the input terminal to aninput of the carrier transistor; a second input line connecting theinput terminal to an input of the peak transistor; a first output lineconnecting the output terminal to an output of the carrier transistor;and a second output line connecting the output terminal to an output ofthe peak transistor.

The present invention solves the problem between the required low Zo (inthe range of 0.5 to 5 Ohm) of the quarter wavelength lines and themicrostrip line technique limitations. It removes the limits implied bymicrostrip lines technique. So, a high power design, essential higherthan 10 W, becomes feasible. Further, the present invention is verysuitable for high power transmitters with peak power levels up to 600 W,such as W-CDMA transmitters.

According to a preferred embodiment of the invention, the first inputline includes an inductor.

According to a preferred embodiment of the invention, the second inputline comprises serial circuits and/or parallel circuits of at least onecapacitance and/or at least one inductance.

According to a preferred embodiment of the invention, the second inputline comprises an inductor.

According to a preferred embodiment of the invention, the first outputline comprises serial circuits and/or parallel circuits of at least onecapacitance and/or at least one inductance.

According to a preferred embodiment of the invention, the first outputline comprises an inductor.

According to a preferred embodiment of the invention, the second outputline comprises an inductor.

According to a preferred embodiment of the invention, the input andoutput networks are artificial transmission lines. The invention isbased upon the insight that artificial transmission lines can be made ina very compact way, even for very low impedance values, below 1 Ohm, andfurther that artificial transmission lines can be easily implementedinside traditional transistor packages. Traditional technology canprovide a high quality factor for this artificial transmission lines atvery low impedance values and perfect repeatability. Another advantageis that the transmission line in low path filter configuration provideadditional harmonic suppression at the output of the main amplifier,serving for better amplifier linearity.

According to a preferred embodiment of the invention, each of thetransistors is operating at its own amplification class. Operating eachtransistor at its own amplification class enables to operate theamplifier at optimal efficiency.

According to a preferred embodiment of the invention, the carriertransistor and the peak transistor have individual transconductanceparameters and threshold voltage values. The individual transconductanceparameters and the individual threshold voltage values of thetransistors enable a very efficient operation of the amplifier.

According to a preferred embodiment of the invention, the carriertransistor output and the peak transistor output are each connected to acompensation circuit. The compensation circuit eliminates the negativeeffects of the parasitic output capacitance of the transistors. Thisleads to an enhanced efficiency of the amplifier in the operationalfrequency band.

According to a preferred embodiment of the invention, the compensationcircuit comprises a serial circuit and/or a parallel circuit of at leastone inductance and/or at least one capacitance.

According to a preferred embodiment of the invention, the carriertransistor and the peak transistor are connected in parallel.

According to a preferred embodiment of the invention, the first inputline and the second input line are connected in parallel.

According to a preferred embodiment of the invention, the first outputline and the second output line are connected in parallel.

According to a preferred embodiment of the invention, the compensationcircuits are connected in parallel.

According to a preferred embodiment of the invention, an impedancetransformation circuit is connected between the input terminal/outputterminal and the input network/output network. The impedancetransformation circuit matches the different impedances of the terminalsto the networks and vice versa.

According to a preferred embodiment of the invention, the impedancetransformation circuit comprises a parallel circuit and/or a serialcircuit of at least one inductance and/or at least one capacitance.

According to a preferred embodiment of the invention, the carriertransistor and the peak transistor are connected to a control circuitproviding the desired dynamic controlling of amplification classparameters of the transistors. The control circuit enhances the powerefficiency or supports an optimal trade-off between efficiency andlinearity of the amplifier.

According to a preferred embodiment of the invention, the amplifier isintegrated in a discrete RF power package. This enables to use thepresent invention in mobile telephones, where a low weight and a smallvolume are essential for application.

To achieve the object of the present invention a high power Dohertyamplifier circuit package is disclosed comprising a support structuresupporting circuit elements of the Doherty amplifier circuit; at leastone input terminal and at least one output terminal both terminals beingsupported on the support structure; at least one carrier transistorforming a main amplifier stage and at least one peak transistor forminga peak amplifier stage both transistors being supported on the supportstructure; a first input network connecting the input terminal to aninput of the carrier transistor; a second input network connecting theinput terminal to an input of the peak transistor; a first outputnetwork connecting the output terminal to an output of the carriertransistor; and a second output network connecting the output terminalto an output of the peak transistor, and wherein the input and outputnetworks are artificial transmission lines comprising serial circuitsand/or parallel circuits of at least one capacitance and/or at least oneinductance. The present invention implements the artificial transmissionlines inside the RF power transistor package close to the powertransistor dies. Than a low characteristic impedance, even below 1 Ohm,can be achieved, allowing a compact design and the Doherty techniqueimplemented in the most efficient way

According to a preferred embodiment of the invention, a compensationcircuit is connected to the output of the transistor. The compensationcircuit enhances the efficiency and/or operational frequency bandwidthof the present invention.

According to a preferred embodiment of the invention, the compensationcircuit comprises a serial circuit and/or a parallel circuit of at leastone inductance and/or at least one capacitance.

According to a preferred embodiment of the invention, the inductancesare made up by bond wires provided between the transistors and the inputand output terminals respectively. It is an advantageous feature of thepresent invention that the bond wires are used as connection and asinductance. This saves costs and space in the layout.

According to a preferred embodiment of the invention, the input networkcomprises parallel bond wires of a given length.

According to a preferred embodiment of the invention, the capacitancesare embodied by a first conducting layer, an insulating layer and asecond conducting layer which is connected to ground.

According to a preferred embodiment of the invention, the transistorsare connected in parallel. It is an advantageous feature that therequired power is provided not only from one transistor, but fromparallel transistors. Therefore, each single transistor contribute apart to the total power. Following, even if there is a single transistorout of order then a total power with a little smaller power value isprovided.

According to a preferred embodiment of the invention, the input networksare connected in parallel. Parallel input networks have the advantagethat the power range input, is divided into several branches of theinput networks. Therefore, the input power of each branch of the inputnetwork which can be operated is reduced.

According to a preferred embodiment of the invention, the outputnetworks are connected in parallel. The advantage of the parallel outputnetworks is in principle analogue to the advantage of the parallel inputnetworks. The output power is divided into several branches. Therefore,the output power of each branch of the output network which can beoperated is reduced.

According to a preferred embodiment of the invention, the compensationcircuits are connected in parallel.

These and various other advantages and features of novelty whichcharacterize the present invention are pointed out with particularity inthe claims annexed hereto and forming a part hereof. However, for abetter understanding of the invention, its advantages, and the objectobtained by its use, reference should be made to the drawings which forma further part hereof, and to the accompanying descriptive matter inwhich there are illustrated and described preferred embodiments of thepresent invention.

FIGS. 1 and 2 show different examples of a compact artificialtransmission line;

FIGS. 3 and 4 show simulated module and phase of S12 in the frequencyband;

FIG. 5 shows the input impedance of the artificial transmission lineversus load at the output;

FIGS. 6A, 6B, 7, 8, and 9 show possible embodiments of the Dohertyamplifier;

FIG. 10 shows the circuit package of FIG. 8;

FIG. 11 shows a circuit package of FIG. 9;

FIG. 12 shows a circuit package of FIG. 6A.

FIG. 13 shows a possible embodiment of the Doherty amplifier;

FIG. 14 shows a circuit package of FIG. 13.

FIG. 1 shows an embodiment of an artificial transmission line which isimplemented inside the RF power transistor package close to the powertransistor dies. The artificial transmission line comprise an inputterminal 2 connected to the inductance 4 having an inductance value of0.33 nH. The inductance 4 is connected on the other side to theinductance 6 having an inductance value of 0.33 nH and to thecapacitance 10 having a capacitance value of 80 pF. The inductance 6 isconnected on the other side to the output terminal 8. The capacitance 10is connected in the other side to ground. Such an artificialtransmission line in general can achieve a very low characteristicimpedance, even below 1 Ohm, allowing a compact design. The artificialtransmission line in theory should provide a phase shift around 90degree within operational frequency band /at 900 MHz/.

FIG. 2 comprises another embodiment of the artificial transmission line.The artificial transmission lines comprises an input terminal 14connected to one side of the capacitance 20, 70 pF, and to one side ofthe inductance 16, 0.36 nH. The capacitance 20 is connected on the otherside to ground 24. The inductance 16 is connected on the other side tothe output terminal 18 and to one side of the capacitance 22, 70 pF. Theother side of the capacitance 22 is connected to ground 26. Thisartificial transmission line provides a 90 degree phase shift at 900 MHzand has a characteristic impedance of 2 Ohm. The artificial transmissionlines shown in FIG. 1 and FIG. 2 can be easily implemented insidetraditional power transistor package. The artificial transmission linein low path filter configuration provides additional harmonicsuppression at the output of the main amplifier/about −10 dB for secondharmonic 2fo/, serving for better carrier amplifier linearity.Traditional technology can provide high quality factor for theseartificial transmission lines at very low impedance values and perfectrepeatability.

The solution where the artificial transmission lines are built withcapacitors, represented by MOS capacitors, and the inductances,represented by parallel gold bond wires, used in the discrete RF powertransistor technology as a connecting media, removes two problems,existing in the Doherty amplifier with traditional microstrip linedesign.

The contradiction is removed between required low Zo, in the range of0.5 to 5 Ohms, of the quarterwave length lines and the microstrip linetechnique limitations. In other words, the present invention removes thelimits implied by distributed microstrip lines technique. So, a highpower design, greater than 10 W, becomes feasible in very compact way.

Another contradiction is removed between the demand for compact designof modem amplifier and the possible size of microstrip lines used forDoherty concept, where the dimensions of the microstrip lines aregrowing drastically with demand for larger output power, which leads tolower required characteristic impedance of 90 degree transmission linetransformer.

FIG. 3 shows the parameter S12 in dB in dependence of the frequency inGHz. The graph shows that up to 1 GHz the S12 parameter is nearlyconstant. Over 1 GHz the scattering parameter S12 slopes linearly downto roughly −11 dB at 2 GHz.

FIG. 4 shows the phase in degree of the scattering parameter S12 independence of the frequency in GHz. The phase slopes down linear from0.8 GHz at a phase of roughly −71° down to roughly −93° at 1 GHz.

FIG. 5 shows the input impedance of the artificial transmission lineversus load at the output. FIG. 5 shows the real and imaginary part ofimpedance seen by transistor die output vs the impedance applied to theartificial line output/in the range of 1 . . . 4 Ohms/. The graphs ofthe real part and of the imaginary part begin at a frequency of 0.8 GHzand end at a frequency of 1.0 GHz. For the impedance of 1 Ohm is onlythe real part shown. The real part of an impedance of 1 Ohm slopes upuntil 0.91 GHz and then the graph slopes down to 1 GHz. The graphs ofthe real parts of other input impedance values slope down linear fromthe frequency of 0.8 GHz down to the frequency of 1.0 GHz. The higherthe real part is the lower is the input impedance. The lowest real partis generally at the end at 1 GHz. The imaginary parts have their minimumin the range of 1 GHz. The imaginary graphs of an input impedance of 3and 4 Ohm slope up linear to the end at 1 GHz. The imaginary graph of aninput impedance of 2 Ohm slopes down to the end at 1 GHz.

FIG. 6A shows a circuit diagram of the present invention. The inputterminal 28 is connected through line 27 to the gate terminal 29 of thetransistor 30. The transistor 30 represents the main amplifier. Thetransistor 30 is shown as an equivalent circuit. The equivalent circuitcomprises a gate resistor 34 connected to the gate terminal 29 and onthe other side connected to the gate source capacitance 38 and to thedrain gate capacitance 36. The drain gate capacitance 36 is connected onthe other side to the current source 40 and to the resistor 42 and tothe output capacitance 44 and to the drain terminal 49. The outputcapacitance 44 is connected on the other side to the other side of theresistor 42, the other side of the current source 40, the other side ofthe gate source capacitance 38 and to the source resistor 46. The sourceresistor 46 is connected to the source terminal 47. The source terminal47 is connected to ground 48. The drain terminal 49 is connected to theoutput terminal 56 through line 33 which is an artificial transmissionline.

The input terminal 28 is connected to the input terminal through line31. The transistor 32 is the peak amplifier. The shown equivalentcircuit of the transistor 32 is identical to the shown equivalentcircuit of the transistor 30. The resistor 64 is equal to the resistor34. The capacitance 68 is identical to the capacitance 38. Thecapacitance 66 is identical to the capacitance 36. The current source 70is identical to the current source 40. The resistor 72 is identical tothe resistor 42. The capacitance 74 is identical to the capacitance 44.The resistor 76 is identical to the resistor 46. The source terminal 77of the transistor 32 is connected to ground 78. The drain terminal 75 ofthe transistor 32 is connected to the output terminal 56 through line 35which is an artificial transmission line.

In the above embodiment, the output parasitic capacitances of thetransistors 30,32 are implemented in artificial transmission line suchas the artificial line shown in FIG. 2, at the output of a Dohertyamplifier. Physically the capacitances of the artificial line areembodied inside of both the peak transistor 32 and main transistor 30dies.

FIG. 6B shows a circuit diagram of the present invention similar to FIG.6A. The input terminal 28 is connected trough line 27 to the gateterminal 29 of the transistor 30. The transistor 30 represents the mainamplifier. The transistor 30 is shown as an equivalent circuit as inFIG. 6A. The drain terminal 49 is connected through line 33 to theoutput terminal 56. The line 33 is an artificial transmission line.

The transmission line 33 comprises an inductance 50 connected to theoutput terminal 49 of the transistor 30. The other side of theinductance 50 is connected to a capacitance 52 and to a inductance 54which, in turn, is connected to the output terminal 56. The capacitance52 is connected to ground.

The input terminal 28 is connected through line 31 to the input terminal63. The line 31 includes an inductance 58. The inductance 58 isconnected on the other side to a capacitance 60 and to an inductance 62.The capacitance 60 is connected on the other side to ground. Theinductance 62 is connected on the other side to the gate terminal 63 ofthe transistor 32. The transistor 32 is the peak amplifier. Theequivalent circuit of the transistor 32 is identical to the shownequivalent circuit of the transistor 30. The inductance 58 and theinductance 62 and the capacitance 60 form an artificial transmissionline. The drain terminal 75 of the transistor 32 is connected to theoutput terminal 56 through line 35 which is an artificial transmissionline.

In the above embodiments, the limitations for low characteristicimpedance of the transmission line and the smaller transmission linesize are removed, and the application frequency band, reproducibility,compact design, and the Doherty amplifier design flexibility isenhanced.

FIG. 7 shows in principle the same circuit as FIG. 6. Therefore, equalnumbers for equal parts are used in FIG. 7. The only difference betweenFIG. 7 and FIG. 6 is that at the drain terminal 49 of transistor 30 andat the drain terminal 75 of the transistor 32 are compensation circuitsapplied. The compensation circuit at terminal 49 comprises a serialcircuit of an inductance 80 and a capacitance 82. The inductance 80 isconnected to the drain terminal 49. The inductance 80 is connected onthe other side to the capacitance 82. The other side of the capacitance82 is connected to ground. The compensation circuit compensates theoutput capacitance 44 of the transistor 30. In principle the same isdone at terminal 75 of transistor 32. The compensation circuitcomprising an inductance 84 and a capacitance 86 compensates the outputcapacitance 74. The compensation circuit is connected with one side ofthe inductance 84 to the terminal 75. The other side of the inductance84 is connected to the capacitance 86. The other side of the capacitance86 is connected to ground. Furthermore, the compensation circuits can beaccomodated as a part of the 90° artificial transmission line.

FIG. 8 shows in principle the same circuit as FIG. 6. But in FIG. 8, theinductance 88 is connected between the input terminal 28 and theterminal 29 and the inductance 90 is connected between the terminal 75and the output terminal 56. The inductances 88 and 90 are formed bybondwires and are used as an input network or an output network Theobject of the input and output network is to match the impedance of thetransistor at the input and output terminals to the impedance at theterminals of the connected other circuit parts. A practical embodimentof FIG. 8 is shown in FIG. 10.

FIG. 9 shows a circuit, which is a combination of the circuits shown anddescribed in FIG. 7 and FIG. 8. The present invention eliminates thecontradiction between possible characteristic impedance of themicrostrip line, lowest possible value is around 10 Ohm, and requiredvalues below 1 Ohm, which is a vital issue for the Doherty amplificationtechnique at high power levels. Further, the present inventioneliminates the contradiction between required physical dimensions of thetransmission lines at the output of the active elements of the Dohertyamplifier and achievable dimensions of the transmission lines in the RFand MW frequency band. Furthermore, the present invention miniaturizesthe Doherty amplifier solution for high power amplifiers with outputpower greater than 10 W. Moreover, the present invention provides aneasy way of Doherty technique implementation using a traditionaltechnology in power amplifiers even at very high power level, greaterthan 300 W, which is impossible with a traditional microstrip linetechnique.

FIG. 10 shows a basic structure as an embodiment of the circuit of FIG.8. The main amplifier transistor die 92 is connected by a plurality ofbond wires 106 to the input lead of the Doherty amplifier 102. The mainamplifier transistor 92 is connected by a plurality of parallel bondwires 110 to the capacitor 94 of the output artificial line. Thecapacitor 94 is connected by a plurality of parallel bond wires 108 tothe output lead 96 of the Doherty amplifier. The peak amplifiertransistor 98 is connected by a plurality of parallel bond wires 112 tothe output lead 96 of the Doherty amplifier. The peak amplifiertransistor 98 is connected by a plurality of parallel bond wires 114 tothe capacitor 100 of the input artificial line. The capacitor 100 isconnected by a plurality of parallel bond wires 116 to the input lead102 of the Doherty amplifier. The circuit is mounted on a support layer104.

FIG. 11 shows a structure of an embodiment of FIG. 9. The main amplifiertransistor die 118 is connected to the input lead 154 of the Dohertyamplifier by a plurality of parallel bond wires 134. The main amplifiertransistor die 118 is connected to the compensation circuit 120 by aplurality of parallel bond wires 136. The output of the main amplifiertransistor die 118 is connected to the capacitor 122 of the outputartificial line by a plurality of parallel bond wires 140. The capacitor122 of the output artificial line is connected to the output lead 124 ofthe Doherty amplifier by a plurality of parallel bond wires 142. Thecompensation circuit 126 is connected to the peak amplifier transistordie 128 via a plurality of parallel bond wires 144.

The peak amplifier transistor die 128 is connected to the output lead124 by a plurality of parallel bond wires 146. The peak amplifier 128 isconnected to the capacitor 130 of the input artificial line by aplurality of parallel bond wires 148. The capacitor 130 is connected tothe input lead 156 of the Doherty amplifier by a plurality of parallelbond wires 150. The input lead 154 and the input lead 156 are concludedto a general input lead 132. The whole before described circuit ismounted on a substrate 152. The present invention is achieved bybuilding an artificial transmission line using an existing traditionaltechnology inside the traditional discrete power transistor packagetogether with a power transistor die and a compensation circuit whichprovide the efficient, flexible and compact solution for very high powerDoherty amplifiers.

FIG. 12 shows a simplified embodiment of the invention corresponding tothe circuit of FIG. 6A. The main amplifier transistor die 292 isconnected by a plurality of bond wires 306 to the input lead of theDoherty amplifier 302. The main amplifier transistor 292 is connected bya plurality of parallel bond wires 310 to output lead 296 of the Dohertyamplifier. The peak amplifier transistor 298 is connected by a pluralityof parallel bond wires 312 to the output lead 296 of the Dohertyamplifier. The peak amplifier transistor 298 is connected by a pluralityof parallel bond wires 314 to the capacitor 300 of the input artificialline. The capacitor 300 is connected by a plurality of parallel bondwires 316 to the input lead 302 of the Doherty amplifier. The circuit ismounted on a support layer 304.

FIG. 13 shows a circuit diagram of the present invention similar to FIG.6B. The input terminal 28 is connected through line 27 to the gateterminal 29 of the transistor 30. The transistor 30 represents the mainamplifier. The transistor 30 is shown as an equivalent circuit as inFIG. 6A. The drain terminal 49 is connected through line 33 comprisingan inductance 400 to the impedance transformation circuit 408. The line33 is an artificial transmission line including the output capacitance44 of the transistor 30.

The impedance transformation circuit 408 comprises an inductance 402connected to the line 33. The other side of the inductance 402 isconnected to a capacitance 406 and to an inductance 404 which, in turn,is connected to the output terminal 56. The capacitance 406 is connectedto ground.

The input terminal 28 is connected through line 31 to the input terminal63. The line 31 includes an inductance 58. The inductance 58 isconnected on the other side to a capacitance 60 and to an inductance 62.The capacitance 60 is connected on the other side to ground. Theinductance 62 is connected on the other side to the gate terminal 63 ofthe transistor 32. The transistor 32 is the peak amplifier. Theequivalent circuit of the transistor 32 is identical to the shownequivalent circuit of the transistor 30. The inductance 58 and theinductance 62 and the capacitance 60 form an artificial transmissionline. The drain terminal 75 of the transistor 32 is connected to theline 33 and to the inductance 402 of the impedance transformationcircuit 408 through line 35 which is an artificial transmission line.

FIG. 14 shows a simplified embodiment of the invention corresponding tothe circuit of FIG. 13. The main amplifier transistor die 500 isconnected by a plurality of bond wires 502 to the input lead 504 of theDoherty amplifier. The main amplifier transistor 500 is connected by aplurality of parallel bond wires 506 to a contact bank 508. The contactbank 508 is connected by a plurality of parallel bond wires 510 to acapacitor 512. The capacitor 512 is connected by a plurality of parallelbond wires 514 to a output lead 516. A peak amplifier transistor 518 isconnected by a plurality of parallel bond wires 520 to the contact bank508 of the Doherty amplifier. The peak amplifier transistor 518 isconnected by a plurality of parallel bond wires 522 to a capacitor 524of the input artificial line. The capacitor 524 is connected by aplurality of parallel bond wires 526 to the input lead 504 of theDoherty amplifier. The circuit is mounted on a support layer 528.

New characteristics and advantages of the invention covered by thisdocument have been set forth in the foregoing description. It will beunderstood, however, that this disclosure is, in many respects, onlyillustrative. Changes may be made in details, particularly in matters ofshape, size, and arrangement of parts, without exceeding the scope ofthe invention. The scope of the invention is, of course, defined in thelanguage in which the appended claims are expressed.

1. A high power Doherty amplifier circuit having at least one inputterminal and at least one output terminal comprising: at least onecarrier transistor forming a main amplifier stage; at least one peaktransistor forming a peak amplifier stage; a first input line connectingthe input terminal to an input of the carrier transistor; a second inputline connecting the input terminal to an input of the peak transistor; afirst output line connecting the output terminal to an output of thecarrier transistor; and a second output line connecting the outputterminal to an output of the peak transistor.
 2. The circuit of claim 1,wherein the first input line includes an inductor.
 3. The circuit ofclaim 1, wherein the second input line comprises serial circuits and/orparallel circuits of at least one capacitance and/or at least oneinductance.
 4. The circuit of claim 3, wherein the second input linecomprises an inductor.
 5. The circuit of claim 1, wherein the firstoutput line comprises serial circuits and/or parallel circuits of atleast one capacitance and/or at least one inductance.
 6. The circuit ofclaim 5, wherein the first output line comprises an inductor.
 7. Thecircuit of claim 1, wherein the second output line comprises aninductor.
 8. The circuit of claim 1, wherein the carrier transistor andthe peak transistor have individual transconductance parameters andthreshold voltage values.
 9. The circuit of claim 1, wherein the carriertransistor output and the peak transistor output are each connected to acompensation circuit.
 10. The circuit of claim 1, wherein an impedancetransformation circuit is connected between the input terminal/outputterminal and the input line/output line.
 11. The circuit of claim 1,wherein the carrier transistor and the peak transistor are connected toa control circuit providing the desired dynamic controlling ofamplification class parameters of the transistors.
 12. A high powerDoherty amplifier circuit package comprising: a support structuresupporting circuit elements of the Doherty amplifier circuit; at leastone input terminal and at least one output terminal both terminals beingsupported on the support structure; at least one carrier transistorforming a main amplifier stage and at least one peak transistor forminga peak amplifier stage both transistors being supported on the supportstructure; a first input line connecting the input terminal to an inputof the carrier transistor; a second input line connecting the inputterminal to an input of the peak transistor; a first output lineconnecting the output terminal to an output of the carrier transistor;and a second output line connecting the output terminal to an output ofthe peak transistor.
 13. The package of claim 12, wherein the input andoutput lines are artificial transmission lines comprising serialcircuits and/or parallel circuits of at least one capacitance and/or atleast one inductance.
 14. The package of claim 12, wherein acompensation circuit is connected to the output of the transistor. 15.The package of claim 12, wherein the compensation circuit comprises aserial circuit and/or a parallel circuit of at least one inductanceand/or at least one capacitance.
 16. The package of claim 12, whereininductances are made up by bond wires provided between the transistorsand the input and output terminals respectively.
 17. The package ofclaim 12, wherein the input lines comprise parallel bond wires of agiven length.
 18. The package of claim 12, wherein capacitances areembodied by a first conducting layer, an insulating layer and a secondconducting layer which is connected to ground.